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ISL6520
TM
Data Sheet
April 2001
File Number
9009.1
Single Synchronous Buck Pulse-Width Modulation (PWM) Controller
The ISL6520 makes simple work out of implementing a complete control and protection scheme for a DC-DC stepdown converter. Designed to drive N-channel MOSFETs in a synchronous buck topology, the ISL6520 integrates the control, output adjustment, monitoring and protection functions into a single 8-pin package. The ISL6520 provides simple, single feedback loop, voltagemode control with fast transient response. The output voltage can be precisely regulated to as low as 0.8V, with a maximum tolerance of 1.5% over temperature and line voltage variations. A fixed frequency oscillator reduces design complexity, while balancing typical application cost and efficiency. The error amplifier features a 15MHz gain-bandwidth product and 8V/s slew rate which enables high converter bandwidth for fast transient performance. The resulting PWM duty cycles range from 0% to 100%. Protection from over-current conditions is provided by monitoring the rDS(ON) of the upper MOSFET to inhibit PWM operation appropriately. This approach simplifies the implementation and improves efficiency by eliminating the need for a current sense resistor.
Features
* Operates from +5V Input * 0.8V to VIN Output Range - 0.8V Internal Reference - 1.5% Over Line Voltage and Temperature * Drives N-Channel MOSFETs * Simple Single-Loop Control Design - Voltage-Mode PWM Control * Fast Transient Response - High-Bandwidth Error Amplifier - Full 0% to 100% Duty Cycle * Lossless, Programmable Over-Current Protection - Uses Upper MOSFET's rDS(on) * Small Converter Size - 300kHz Fixed Frequency Oscillator - Internal Soft Start - 8-Lead SOIC Package
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Applications
* Power Supplies for Microprocessors - PCs - Embedded Controllers * Subsystem Power Supplies - PCI/AGP/GTL+ Buses - ACPI Power Control * Cable Modems, Set Top Boxes, and DSL Modems * DSP and Core Communications Processor Supplies * Memory Supplies * Personal Computer Peripherals * Industrial Power Supplies * 5V-Input DC-DC Regulators * Low-Voltage Distributed Power Supplies
Ordering Information
PART NUMBER TEMP. RANGE (oC) 0 to 70 -40 to 85 PACKAGE 8 Ld SOIC 8 Ld SOIC PKG. NO. M8.15 M8.15
rsi por n, ico cto pi, er ag nt, nt lab d ag
ISL6520CB ISL6520IB ISL6520EVAL1
Evaluation Board
Pinout
BOOT 1 UGATE 2 GND 3 LGATE 4 8 PHASE 7 COMP/OCSET 6 FB 5 VCC
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 321-724-7143 | Intersil and Design is a trademark of Intersil Americas Inc. Copyright (c) Intersil Americas Inc. 2001, All Rights Reserved
ISL6520 Block Diagram
VCC
SAMPLE AND HOLD
+ OC COMPARATOR
-
POR AND SOFTSTART
BOOT UGATE
PHASE + 0.8V ERROR AMP + PWM COMPARATOR INHIBIT
FB COMP/OCSET 20A
-
+
-
GATE CONTROL LOGIC PWM
VCC
LGATE
OSCILLATOR FIXED 300kHz GND
Typical Application
VCC
CDCPL
CBULK DBOOT 1 BOOT CBOOT LOUT
CHF
VCC ROCSET 5
ISL6520
COMP/OCSET 7 RF CI CF FB 6 3 GND 4 2 8
UGATE PHASE
+VO
LGATE
COUT
ROFFSET
RS
2
ISL6520
Absolute Maximum Ratings
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6.0V Absolute Boot Voltage, VBOOT . . . . . . . . . . . . . . . . . . . . . . . +15.0V Upper Driver Supply Voltage, VBOOT - VPHASE . . . . . . . . . . . +6.0V Input, Output or I/O Voltage . . . . . . . . . . . GND -0.3V to VCC +0.3V ESD Classification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Class 2
Thermal Information
Thermal Resistance (Typical, Note 1) JA ( oC/W) SOIC Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 Maximum Junction Temperature . . . . . . . . . . . . . . . . . . . . . . 150oC Maximum Storage Temperature Range . . . . . . . . . . -65oC to 150oC Maximum Lead Temperature (Soldering 10s) . . . . . . . . . . . . 300oC (SOIC - Lead Tips Only)
Operating Conditions
Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . +5V 10% Ambient Temperature Range . . . . . . . . . . . . . . . . . . . -40oC to 85oC Junction Temperature Range. . . . . . . . . . . . . . . . . . -40oC to 125oC
CAUTION: Stresses above those listed in "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied.
NOTE: 1. JA is measured with the component mounted on a low effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER VCC SUPPLY CURRENT Nominal Supply POWER-ON RESET Rising VCC POR Threshold VCC POR Threshold Hysteresis OSCILLATOR Frequency
Recommended Operating Conditions, Unless Otherwise Noted. VCC = 5.0V 5% and TA = 25oC SYMBOL TEST CONDITIONS MIN TYP MAX UNITS
IVCC POR
UGATE and LGATE Open
2.6
3.2
3.8
mA
4.19 0.01
4.30 0.20
4.5 0.85
V V
fOSC VOSC VREF
ISL6520CB, VCC = 5V ISL6520IB, VCC = 5V
250 230 -
300 300 1.5
340 340 -
kHz kHz VP-P % V
Ramp Amplitude REFERENCE Reference Voltage Tolerance Nominal Reference Voltage ERROR AMPLIFIER DC Gain Gain-Bandwidth Product Slew Rate
-
0.800
1.5 -
GBWP SR ISL6520CB, COMP = 10pF ISL6520IB, COMP = 10pF 14 4.65 4.5
82 8.0 8.0
9.2 9.2
dB MHz V/s V/s
GATE DRIVERS Upper Gate Source Current Upper Gate Sink Current Lower Gate Source Current Lower Gate Sink Current PROTECTION / DISABLE OCSET Current Source IOCSET VDISABLE ISL6520CB ISL6520IB Disable Threshold 17 14 20 20 22 24 0.8 A A V IUGATE-SRC IUGATE-SNK ILGATE-SRC ILGATE-SNK -1 1 -1 2 A A A A
3
ISL6520 Functional Pin Description
VCC (Pin 5)
This is the main bias supply for the ISL6520, as well as the lower MOSFET's gate. Connect a well-decoupled 5V supply to this pin. An over-current trip cycles the soft-start function. During soft-start, and all the time during normal converter operation, this pin represents the output of the error amplifier. Use this pin, in combination with the FB pin, to compensate the voltage-control feedback loop of the converter. Pulling OCSET to a level below 0.8V will disable the controller. Disabling the ISL6520 causes the oscillator to stop, the LGATE and UGATE outputs to be held low, and the softstart circuitry to re-arm.
FB (Pin 6)
This pin is the inverting input of the internal error amplifier. Use this pin, in combination with the COMP/OCSET pin, to compensate the voltage-control feedback loop of the converter.
GND (Pin 3)
This pin represents the signal and power ground for the IC. Tie this pin to the ground island/plane through the lowest impedance connection available.
LGATE (Pin 4)
Connect this pin to the lower MOSFET's gate. This pin provides the PWM-controlled gate drive for the lower MOSFET. This pin is also monitored by the adaptive shoot-through protection circuitry to determine when the lower MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the lower MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective.
PHASE (Pin 8)
Connect this pin to the upper MOSFET source. This pin is used to monitor the voltage drop across the upper MOSFET for over-current protection. This pin is also monitored by the continuously adaptive shoot-through protection circuitry to determine when the upper MOSFET has turned off.
Functional Description
Initialization
The ISL6520 automatically initializes upon receipt of power. The Power-On Reset (POR) function continually monitors the bias voltage at the VCC pin. The POR function initiates the Over-Current Protection (OCP) sampling and hold operation after the supply voltage exceeds its POR threshold. Upon completion of the OCP sampling and hold operation, the POR function initiates the Soft Start operation.
UGATE (Pin 2)
Connect this pin to the upper MOSFET's gate. This pin provides the PWM-controlled gate drive for the upper MOSFET. This pin is also monitored by the adaptive shootthrough protection circuitry to determine when the upper MOSFET has turned off. Do not insert any circuitry between this pin and the gate of the upper MOSFET, as it may interfere with the internal adaptive shoot-through protection circuitry and render it ineffective.
Over Current Protection
The over-current function protects the converter from a shorted output by using the upper MOSFET's on-resistance, rDS(ON), to monitor the current. This method enhances the converter's efficiency and reduces cost by eliminating a current sensing resistor. The over-current function cycles the soft-start function in a hiccup mode to provide fault protection. A resistor (ROCSET) programs the over-current trip level (see Typical Application diagram). Immediately following POR, the ISL6520 initiates the OverCurrent Protection sampling and hold operation. First, the internal error amplifier is disabled. This allows an internal 20A current sink to develop a voltage across ROCSET. The ISL6520 then samples this voltage at the COMP pin. This sampled voltage,which is referenced to the VCC pin, is held internally as the Over-Current Set Point. When the voltage across the upper MOSFET, which is also referenced to the VCC pin, exceeds the Over-Current Set Point, the over-current function initiates a soft-start sequence. Figure 1 shows the inductor current after a fault is introduced while running at 15A. The continuous fault causes the ISL6520 to go into a hiccup mode with a typical period of 25ms. The inductor current increases to 18A during the Soft
BOOT (Pin 1)
This pin provides ground referenced bias voltage to the upper MOSFET driver. A bootstrap circuit is used to create a voltage suitable to drive a logic-level N-channel MOSFET.
COMP/OCSET (Pin 7)
This is a multiplexed pin. During a short period of time following power-on reset (POR), this pin is used to determine the overcurrent threshold of the converter. Connect a resistor (ROCSET) from this pin to the drain of the upper MOSFET (VCC). ROCSET, an internal 20A current source (IOCSET), and the upper MOSFET on-resistance (rDS(ON)) set the converter overcurrent (OC) trip point according to the following equation:
IOCSET xR OCSET I PEAK = -----------------------------------------------r D S ( ON )
Internal circuitry of the ISL6520 will not recognize a voltage drop across ROCSET larger than 0.5V. Any voltage drop across R OCSET that is greater than 0.5V will set the overcurrent trip point to:
0.5V I PEAK = ---------------------r DS ( ON )
4
ISL6520
Start interval and causes an over-current trip. The converter dissipates very little power with this method. The measured input power for the conditions of Figure 1 is only 1.5W. internally generated Soft Start voltage exceeds the feedback (FB pin) voltage, the output voltage is in regulation. This method provides a rapid and controlled output voltage rise. The entire startup sequence typically take about 11ms.
OUTPUT INDUCTOR CURRENT 5A/DIV. VOUT 500mV/DIV. COMP/OCSET 1V/DIV.
TIME (5ms/DIV.)
FIGURE 1. OVERCURRENT OPERATION
TIME (2ms/DIV.)
FIGURE 2. START UP SEQUENCE
The over-current function will trip at a peak inductor current (IPEAK) determined by:
IOCSET x R OCSET I PEAK = ---------------------------------------------------r DS ( ON )
Application Guidelines
Layout Considerations
As in any high frequency switching converter, layout is very important. Switching current from one power device to another can generate voltage transients across the impedances of the interconnecting bond wires and circuit traces. These interconnecting impedances should be minimized by using wide, short printed circuit traces. The critical components should be located as close together as possible, using ground plane construction or single point grounding.
VIN
where IOCSET is the internal OCSET current source (20A typical). The OC trip point varies mainly due to the MOSFET's rDS(ON) variations. To avoid over-current tripping in the normal operating load range, find the R OCSET resistor from the equation above with: 1. The maximum rDS(ON) at the highest junction temperature. 2. The minimum IOCSET from the specification table. 3. Determine IPEAK for
( I ) IPEAK > IOUT ( MAX ) + --------- , 2
where I is the output inductor ripple current. For an equation for the ripple current see the section under component guidelines titled `Output Inductor Selection'.
ISL6520
UGATE PHASE Q2 Q1
LO
VOUT
Soft Start
The POR function initiates the soft start sequence after the overcurrent set point has been sampled. Soft start clamps the error amplifier output (COMP pin) and reference input (noninverting terminal of the error amp) to the internally generated Soft Start voltage. Figure 2 shows a typical start up interval where the COMP/OCSET pin has been released from a grounded (system shutdown) state. Initially, the COMP/OCSET is used to sample the oversurrent setpoint by disabling the error amplifier and drawing 20A through ROCSET. Once the overcurrent level has been sampled, the soft start function is initiated. The clamp on the error amplifier (COMP/OCSET pin) initially controls the converter's output voltage during soft start. The oscillator's triangular waveform is compared to the ramping error amplifier voltage. This generates PHASE pulses of increasing width that charge the output capacitor(s). When the 5
LGATE CO LOAD CIN
RETURN
FIGURE 3. PRINTED CIRCUIT BOARD POWER AND GROUND PLANES OR ISLANDS
Figure 3 shows the critical power components of the converter. To minimize the voltage overshoot, the interconnecting wires indicated by heavy lines should be part of a ground or power plane in a printed circuit board. The components shown in Figure 3 should be located as close together as possible. Please note that the capacitors CIN and CO may each
ISL6520
represent numerous physical capacitors. Locate the ISL6520 within 3 inches of the MOSFETs, Q1 and Q2 . The circuit traces for the MOSFETs' gate and source connections from the ISL6520 must be sized to handle up to 1A peak current. Figure 4 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP/OCSET pin and locate the resistor, ROSCET close to the COMP/OCSET pin because the internal current source is only 20A. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. All components used for feedback compensation should be located as close to the IC a practical.
BOOT +5V CBOOT +VIN D1 Q1 LO VOUT LOAD VE/A +
2. Place 1ST Zero Below Filter's Double Pole (~75% FLC). 3. Place 2ND Zero at Filter's Double Pole. 4. Place 1ST Pole at the ESR Zero. 5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error Amplifier's Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary.
OSC PWM COMPARATOR VOSC
DRIVER
VIN LO VOUT CO
-
+
DRIVER
PHASE
ZFB
ESR (PARASITIC)
-
ZIN REFERENCE
ROCSET
ISL6520
PHASE VCC +5V Q2 CVCC CO
ERROR AMP
COMP/OCSET
DETAILED COMPENSATION COMPONENTS ZFB ZIN R2 C3 R1 FB R3 VOUT
GND C1
C2
FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES
COMP
+
-
Feedback Compensation
Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulsewidth modulated (PWM) wave with an amplitude of V IN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO).
ISL6520 REFERENCE
FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN
Modulator Break Frequency Equations
1 FLC = -----------------------------------------2 x L x C O O 1 FESR = ------------------------------------------2 x ESR x C O
The modulator transfer function is the small-signal transfer function of VOUT/VE/A . This function is dominated by a DC Gain and the output filter (LO and CO ), with a double pole break frequency at F LC and a zero at FESR . The DC Gain of the modulator is simply the input voltage (VIN ) divided by the peak-to-peak oscillator voltage VOSC .
Compensation Break Frequency Equations
1 F Z1 = ----------------------------------2 x R 2 x C1 1 FP1 = -------------------------------------------------------C1 x C2 2 x R 2 x --------------------C1 + C2 1 FP2 = ----------------------------------2 x R 3 x C 3

The compensation network consists of the error amplifier (internal to the ISL6520) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network's poles, zeros and gain to the components (R 1 , R 2 , R3 , C 1 , C2 , and C 3) in Figure 7. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth.
1 F Z2 = -----------------------------------------------------2 x (R1 + R3) x C3
Figure 6 shows an asymptotic plot of the DC-DC converter's gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain.
6
ISL6520
Check the compensation gain at FP2 with the capabilities of the error amplifier. The Closed Loop Gain is constructed on the graph of Figure 6 by adding the Modulator Gain (in dB) to the Compensation Gain (in dB). This is equivalent to multiplying the modulator transfer function to the compensation transfer function and plotting the gain. The compensation gain uses external impedance networks ZFB and ZIN to provide a stable, high bandwidth (BW) overall loop. A stable control loop has a gain crossing with -20dB/decade slope and a phase margin greater than 45 degrees. Include worst case component variations when determining phase margin. Use only specialized low-ESR capacitors intended for switching-regulator applications for the bulk capacitors. The bulk capacitor's ESR will determine the output ripple voltage and the initial voltage drop after a high slew-rate transient. An aluminum electrolytic capacitor's ESR value is related to the case size with lower ESR available in larger case sizes. However, the Equivalent Series Inductance (ESL) of these capacitors increases with case size and can reduce the usefulness of the capacitor to high slew-rate transient loading. Unfortunately, ESL is not a specified parameter. Work with your capacitor supplier and measure the capacitor's impedance with frequency to select a suitable component. In most cases, multiple electrolytic capacitors of small case size perform better than a single large case capacitor.
100 80 60 GAIN (dB) 40 20 0 -20 -40 20LOG (R2/R1) MODULATOR GAIN
FZ1 FZ2
FP1
FP2 OPEN LOOP ERROR AMP GAIN
Output Inductor Selection
The output inductor is selected to meet the output voltage ripple requirements and minimize the converter's response time to the load transient. The inductor value determines the converter's ripple current and the ripple voltage is a function of the ripple current. The ripple voltage and current are approximated by the following equations:
I = VIN - VOUT Fs x L x VOUT VIN VOUT = I x ESR
20LOG (VIN/DVOSC) COMPENSATION GAIN CLOSED LOOP GAIN FESR 10K 100K 1M 10M
FLC -60 10 100 1K
FREQUENCY (Hz)
FIGURE 6. ASYMPTOTIC BODE PLOT OF CONVERTER GAIN
Increasing the value of inductance reduces the ripple current and voltage. However, the large inductance values reduce the converter's response time to a load transient. One of the parameters limiting the converter's response to a load transient is the time required to change the inductor current. Given a sufficiently fast control loop design, the ISL6520 will provide either 0% or 100% duty cycle in response to a load transient. The response time is the time required to slew the inductor current from an initial current value to the transient current level. During this interval the difference between the inductor current and the transient current level must be supplied by the output capacitor. Minimizing the response time can minimize the output capacitance required. The response time to a transient is different for the application of load and the removal of load. The following equations give the approximate response time interval for application and removal of a transient load:
tRISE = L x ITRAN VIN - VOUT tFALL = L x ITRAN VOUT
Component Selection Guidelines
Output Capacitor Selection
An output capacitor is required to filter the output and supply the load transient current. The filtering requirements are a function of the switching frequency and the ripple current. The load transient requirements are a function of the slew rate (di/dt) and the magnitude of the transient load current. These requirements are generally met with a mix of capacitors and careful layout. Modern components and loads are capable of producing transient load rates above 1A/ns. High frequency capacitors initially supply the transient and slow the current load rate seen by the bulk capacitors. The bulk filter capacitor values are generally determined by the ESR (Effective Series Resistance) and voltage rating requirements rather than actual capacitance requirements. High frequency decoupling capacitors should be placed as close to the power pins of the load as physically possible. Be careful not to add inductance in the circuit board wiring that could cancel the usefulness of these low inductance components. Consult with the manufacturer of the load on specific decoupling requirements.
where: ITRAN is the transient load current step, tRISE is the response time to the application of load, and tFALL is the response time to the removal of load. The worst case response time can be either at the application or removal of load. Be sure to check both of these equations at the
7
ISL6520
minimum and maximum output levels for the worst case response time. to package thermal-resistance specifications. A separate heatsink may be necessary depending upon MOSFET power, package type, ambient temperature and air flow.
PUPPER = Io2 x rDS(ON) x D + 1 Io x VIN x tSW x FS 2
Input Capacitor Selection
Use a mix of input bypass capacitors to control the voltage overshoot across the MOSFETs. Use small ceramic capacitors for high frequency decoupling and bulk capacitors to supply the current needed each time Q 1 turns on. Place the small ceramic capacitors physically close to the MOSFETs and between the drain of Q1 and the source of Q2 . The important parameters for the bulk input capacitor are the voltage rating and the RMS current rating. For reliable operation, select the bulk capacitor with voltage and current ratings above the maximum input voltage and largest RMS current required by the circuit. The capacitor voltage rating should be at least 1.25 times greater than the maximum input voltage and a voltage rating of 1.5 times is a conservative guideline. The RMS current rating requirement for the input capacitor of a buck regulator is approximately 1/2 the DC load current. For a through hole design, several electrolytic capacitors may be needed. For surface mount designs, solid tantalum capacitors can be used, but caution must be exercised with regard to the capacitor surge current rating. These capacitors must be capable of handling the surge-current at power-up. Some capacitor series available from reputable manufacturers are surge current tested.
PLOWER = Io2 x rDS(ON) x (1 - D) Where: D is the duty cycle = VOUT / VIN , tSW is the switching interval, and FS is the switching frequency.
Given the reduced available gate bias voltage (5V), logic-level or sub-logic-level transistors should be used for both N-MOSFETs. Caution should be exercised with devices exhibiting very low V GS(ON) characteristics. The shoot-through protection present aboard the ISL6520 may be circumvented by these MOSFETs if they have large parasitic impedences and/or capacitances that would inhibit the gate of the MOSFET from being discharged below its threshold level before the complementary MOSFET is turned on.
+5V DBOOT + VD BOOT +5V
VCC
ISL6520
UGATE PHASE
CBOOT Q1 NOTE: VG-S VCC -VD Q2 NOTE: VG-S VCC GND
MOSFET Selection/Considerations
The ISL6520 requires two N-Channel power MOSFETs. These should be selected based upon rDS(ON) , gate supply requirements, and thermal management requirements. In high-current applications, the MOSFET power dissipation, package selection and heatsink are the dominant design factors. The power dissipation includes two loss components; conduction loss and switching loss. The conduction losses are the largest component of power dissipation for both the upper and the lower MOSFETs. These losses are distributed between the two MOSFETs according to duty factor (see the equations below). Only the upper MOSFET has switching losses, since the lower MOSFETs body diode or an external Schottky rectifier across the lower MOSFET clamps the switching node before the synchronous rectifier turns on. These equations assume linear voltage-current transitions and do not adequately model power loss due the reverse-recovery of the lower MOSFET's body diode. The gate-charge losses are dissipated by the ISL6520 and don't heat the MOSFETs. However, large gate-charge increases the switching interval, tSW which increases the upper MOSFET switching losses. Ensure that both MOSFETs are within their maximum junction temperature at high ambient temperature by calculating the temperature rise according 8
+
-
LGATE
FIGURE 7. UPPER GATE DRIVE BOOTSTRAP
Figure 7 shows the upper gate drive (BOOT pin) supplied by a bootstrap circuit from V CC. The boot capacitor, CBOOT, develops a floating supply voltage referenced to the PHASE pin. The supply is refreshed to a voltage of V CC less the boot diode drop (V D) each time the lower MOSFET, Q2, turns on.
ISL6520 ISL6520 DC-DC Converter Application Circuit
Figure 8 shows an application circuit of a DC-DC Converter. Detailed information on the circuit, including a complete Billof-Materials and circuit board description, can be found in Application Note AN9932.
+5V 0.1F + CIN 2 x 330F VCC 6.19k ISL6520 5 MONITOR AND PROTECTION COMP/OCSET 7 REF 10.0k 470pF 8200pF FB 6 OSC 1.00k U1 3 GND 3.16k + 1 BOOT D1 2 x 1F
2 UGATE 8 PHASE Q1
0.1F L1 VOUT
-
+
4
LGATE Q2 + COUT 3 x 330F 0.1F
-
60.4
18000pF
Component Selection Notes: CIN - Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent. COUT - Each 330mF 6.3WVDC, Sanyo 6TPB330M or Equivalent. D1 - 30mA Schottky Diode, MA732 or Equivalent L1 - 3.1H Inductor, Panasonic P/N ETQ-P6F2ROLFA or Equivalent. Q1 , Q2 - Intersil MOSFET; HUF76143.
FIGURE 8. 5V to 3.3V 15A DC-DC CONVERTER
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ISL6520 Small Outline Plastic Packages (SOIC)
N INDEX AREA E -B1 2 3 SEATING PLANE -AD -CA h x 45o H 0.25(0.010) M BM
M8.15 (JEDEC MS-012-AA ISSUE C)
8 LEAD NARROW BODY SMALL OUTLINE PLASTIC PACKAGE INCHES SYMBOL A
L
MILLIMETERS MIN 1.35 0.10 0.33 0.19 4.80 3.80 MAX 1.75 0.25 0.51 0.25 5.00 4.00 NOTES 9 3 4 5 6 7 8o Rev. 0 12/93
MIN 0.0532 0.0040 0.013 0.0075 0.1890 0.1497
MAX 0.0688 0.0098 0.020 0.0098 0.1968 0.1574
A1 B C D E

A1 0.10(0.004) C
e H h L N
0.050 BSC 0.2284 0.0099 0.016 8 0o 8o 0.2440 0.0196 0.050
1.27 BSC 5.80 0.25 0.40 8 0o 6.20 0.50 1.27
e
B 0.25(0.010) M C AM BS
NOTES: 1. Symbols are defined in the "MO Series Symbol List" in Section 2.2 of Publication Number 95. 2. Dimensioning and tolerancing per ANSI Y14.5M-1982. 3. Dimension "D" does not include mold flash, protrusions or gate burrs. Mold flash, protrusion and gate burrs shall not exceed 0.15mm (0.006 inch) per side. 4. Dimension "E" does not include interlead flash or protrusions. Interlead flash and protrusions shall not exceed 0.25mm (0.010 inch) per side. 5. The chamfer on the body is optional. If it is not present, a visual index feature must be located within the crosshatched area. 6. "L" is the length of terminal for soldering to a substrate. 7. "N" is the number of terminal positions. 8. Terminal numbers are shown for reference only. 9. The lead width "B", as measured 0.36mm (0.014 inch) or greater above the seating plane, shall not exceed a maximum value of 0.61mm (0.024 inch). 10. Controlling dimension: MILLIMETER. Converted inch dimensions are not necessarily exact.
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